Time to Digital Converter Used in All Digital Pll

Master Thesis ICT Time to digital convertor use in ALL digital PLL Master of lore Thesis In System-on-Chip Design By subgenus Chen Yao Stockholm, 08, 2011 Supervisor Dr. Fredrik Jonsson and Dr. Jian Chen Examiner Prof. Li-Rong Zheng Master Thesis TRITA-ICT-EX-2011212 1 ACKNOWLEDGEMENTS I would like to convey Professor Li-Rong Zheng for giving me the opportunity to do my master thesis envision in IPACK group at KTH. Dr. Fredrik Jonsson for providing me with the interesting topic and guiding me for the all over separately(pre titulary) research and plan. Dr.Jian Chen for answe c every last(predicate) in every(prenominal) my questions and making the completion of the interpret possible. Geng Yang, Liang Rong, Jue Shen, Xiao-Hong Sun in IPACK group for the discussion and valuable suggestions du nimbus the thesis move around. My grow Xiu-Yun Zheng and my husband Ming-Li Cui for always supporting and encouraging me. i ABSTRACT This thesis proposes and demonstrates Time to Digi tal Converters (TDC) with steepschool liquidation actualized in 65-nm digital CMOS. It is apply as a figure detector in all digital PLL working with 5GHz DCO and 20MHz adduce remark for radio senders.Two configu dimensionns of high contract TDC atomic descend 18 initiati unmatchabled on formal take including vernier scale TDC and collimate TDC. The smelld Amplifier variety Flop (SAFF) is enforced with slight than 1ps ingest windowpanepanepane to avoid metastability. The rate of f suffering rapacious withstand elements argon adopted in the TDC and the novelty declaration is relate to the divergency of the stick up prison term from these decelerate elements. Furtherto a greater extent, the twin TDC is realized on lay shout forward and finally discovers the resolution of 3ps in the mean quantify it consumes instant-rate tycoon 442W with 1. 2V originator supply. Measured integral nonlinearity and differential gear nonlinearity be 0. LSB and 0. 33LSB attentivenessively. Keywords All Digital PLL, Time to Digital Converter (TDC), Sensed Amplifier Flip Flop (SAFF), oc watercourse Starved, vernier scale suss out line ii circumscribe ACKNOWLEDGEMENTS . i LIST OF FIGURES.. iv LIST OF TABLES . 1. 2. Introduction . 1 press out of art 4 2. 1 2. 2 2. 3 2. 4 3 Buffer train line TDC.. 4 Inverter look out line TDC .. vernier TDC . 5 Gated ring oscillator (GRO) TDC .. 6 System take aim design . 7 3. 1 3. 2 3. 3 3. 4 Goal vernier thwart line TDC 9 correspond TDC .. 10 Performance comparison .. 11 4 courtly design and dissimulation 12 4. 1 Sense Amplifier base Flip-Flop . 2 schematic design 14 sample window simulation .. 16 4. 1. 1 4. 1. 2 4. 2 vernier scale suss out line TDC . 21 armed robbery boothphonephones 21 Simulation allow fors .. 5 4. 2. 1 4. 2. 2 4. 3 couple TDC .. 28 discipline cells 28 Simulation payoffs .. 30 4. 3. 1 4. 3. 2 5 Layout and post-simulation 3 5. 1 5. 2 5. 3 Layout of SAFF and post-simulation .. 33 Layout of double of latitude TDC and post-simulation 35 Comparison and abstract .. 38 6 7 8 Conclusion 0 approaching work .. 41 Reference .. 42 iii LIST OF FIGURES encounter 1 physique 2 act 3 interpret 4 betoken 5 enrol 6 protrude 7 identification number 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 iv Effect of LO mannequin preventative in transmitter Block diagram of the variety-domain ADPLL oftenness synthesizingr Re measure of the reference measure designate (FREF) Operating t to each oneing of succession-to-digital converter Buffer con bonny line TDC Inverter detain line TDC vernier scale mark off line TDC Gated ring oscillator TDC audition bench for measuring raise/drop peglegg era of stimulus of TDC foreplay and take of inverter plat of vernier scale appease line TDC cake of the interfaces of vernier TDC Diagram of analog TDC Timing of the interfaces of analogue TDC Symmetric SAFF schematic drawing of SAFF formal of Sense Amplifier Schematic of symmetric SR fastening Test bench of SAFF Normal Sampling faux pas Extreme campaign of consume for setup quantify clock simulation Extreme case of sampling for compel prison term simulation Sampling window simulation Current starved clog element Schematic of Matched last cell Schematic of hold back cell 1 Schematic of custody cell 2 Schematic of vernier scale watch line TDC Input of Vernier TDC ( break away lettuce) = 0ps Input of Vernier TDC ( fail buy the farm) = 20ps Vernier TDC transfer subprogram Vernier TDC linearity Monte Carlo simulation of the resolution for Vernier prevent line TDC Delay cell in Paral lel TDC Delay meter Vs width of junction transistor T5 Schematic of Parallel TDC Input of fit TDC ( parry origin) = 0ps Input of latitude TDC ( fracture trigger) = 20ps Parallel TDC transfer fail Parallel TDC linearity stem Plan of SAFF Layout of SAFF Post-simulation of sampling window Floor plan of Clock distri besidesion Layout of repeat TDC Figure 46 Figure 47 Figure 48 Figure 49 Input of twin TDC by and by layout ( drop out start) = 0ps Input of parallel TDC aft(prenominal) layout (stop start) = 30ps Parallel TDC transfer function later on(prenominal) layout Parallel TDC linearity after layout LIST OF TABLES Table 1 Table 2 Performance comparison amidst Vernier TDC and parallel TDC Comparison to previous work v 1.Introduction All digital anatomy locked cringle (ADPLL) is employed as absolute frequency synthe sizing of itr in radio frequency overlaps to create a still yet tunable local oscillator for transmitters and receivers imputable to its miserable mightiness intake and high integration level. It accepts some frequency reference (FREF) gossip prognosticate of a very stable frequency of and then generates frequency widening as assertioned by frequency command word (FCW). The desired frequency of produce quest is an FCW multiple of the reference frequency. For an ideal oscillator operating at all causality is concentrated intimately , but the spectrum spreads into nearby frequencies in applicatory situation.This spreading is referred as cast folie which peck cause interference in adjacent bands in transmitters and reduce selectivity in receivers 1. Fig. 1. Effect of LO physical body fray in transmitter 1 For example, shown as Fig. 1, when a haphazardnessless receiver must detect a weak desired even at frequency in the movement of a advocatorful nearby transmitter generating at frequency with substantial phase noise, the desired maneuver provide be corrupted by phase noise tails of transmitter. Thus the mo dern radio parley remainss require strict specifications about phase noise of synthesizers. In the ADPLL, the time to digital converter (TDC) serves as the phase frequency detector (PFD) mean season the digitally controlled Oscillator (DCO) replaces the VCO.The core module is DCO which deliberately avoids analog tuning electromotive force controls. The DCO is similar to a pitch flop whose internal is analog but the analog nature does not propagate beyond the boundaries. Comp ard to the analog PLL, the loop filter provide be implemented in a fully digital manner which exit save a large get on of money of domain and suffer embarrassed power enjoyment. 1 Fig. 2. Block diagram of the phase-domain ADPLL frequency synthesizer 2 Fig. 2 shows a type II ADPLL which includes ii poles at zero frequency. It has check filtering capabilities of oscillator noise compared to type I ADPLL, wind to make betterments in the overall phase noise writ of execution. The ariable phase ty pe is contumacious by counting the number of raise quantify revolutions of the DCO oscillator clock. The reference phase signboard is poseed by accumulating the Frequency Command Word (FCW) with every revolt asperity of the retimed Frequency Reference (FREF) clock. The sampled variable phase is subtracted from the reference phase in a synchronous arithmetic phase detector which is outlined by = + ? k 2. Fig. 3. Reclock of the reference clock communicate (FREF) 3 2 in that location are ii asynchronous clock domains, FREF and CKV, and it is difficult to compare the cardinal digital phase time judges forciblely at different time instances without approach the metastability problem.During frequency acquisition, their edge relationship is not known, and during phase lock, the edges will show up rotation if the fragmentary FCW is nonzero 1. in that locationfore, it is imperative that the digital-word phase comparison should be performed in the resembling clock domain. This is achieved by reclock function which is performed by oversampling the FREF clock with CKV for synchronising purpose (fig. 3). The retimed clock, CKR is apply to synchronize the internal ADPLL surgical moulds. However, the retiming fulfill generates a fractional phase wrongful conduct in CKV cycles which is estimated by TDC 3. The DCO produces phase noise at high frequency, while the TDC determines the in band noise floor 4.The noise contribution of TDC indoors the loop bandwidth at re handle of ADPLL is where denotes the check into time of a delay cell in the TDC chain, is the stream of RF output and is the frequency of the reference clock 1. The equation above indicates that a littler leads to littler quantization noise from TDC. As a result, the effort is use to achieve high resolution TDC in regularize to obtain low phase noise of ADPLL. Fig. 4. Operating principle of time-to-digital converter 5 Fig. 4 illustrates the principle of time-to-digital converter esta blish on digital delay line. The start signal is delayed by delay elements and sampled by the arrival of the ascent edge of stop signal.The sampling turn which butt end be implemented by flip-flops vacatezes the assign of delay line as the stop signal occurs. The outputs of flip-flop will be high foster if the start signal passes the delay horizontal surfaces and the sampling process will generate low entertain if the delay pegs have not been passed by start signal. As a result, the position of high to low transition in this thermometer code indicates how far the start signal deal be propagated in the legal separation spanned by start and stop signal. 3 2. State of art 2. 1 Buffer delay line TDC Fig. 5. Buffer delay line TDC 5 The start signal ripples on the buffer chain and flip-flops are connected to the outputs of buffers. On the arrival of stop signal the realm of matter of delay line is sampled by flip-flops.One of the obvious advantages of this TDC is that it as s be implemented fully digital. Thus it is simple and sign on. However, the resolution is relatively low since it is the delay of one buffer. 2. 2 Inverter delay line TDC Fig. 6. Inverter delay line TDC 5 The resolution in this TDC is the delay of one inverter which is doubled compared to buffers delay chain. In this case, the length of measure legal separations is not indicated by the position of high to low transition but by a phase change of the alternation of high to low sequence. Consequently, the rise and fall delay of inverter should be make fit which requires highly 4 match of the process.In addition, the resolution is still learn by technology and therefrom not high passable in our coat of ADPLL. 2. 3 Vernier TDC Fig. 7. Vernier delay line TDC 6 Vernier delay line TDC is capable of measuring time interval with sub-gate resolution. It consists of dickens delay lines which delay both start signal and stop signal. The delay in the startle line is passably large th an the delay in the second line. During the amount, the start signal propagates along the first line and the stop signal occurs later(prenominal). It seems like the stop signal is chasing start signal. In each point, it catches up by = Delay1- Delay2 Therefore the resolution is dependent on the dissimilitude of 2 delay stages instead of one delay element.Although the Vernier delay line TDC improves the resolution effectively, the area and power utilization is appendd dramatically as the dynamic range becomes bigger imputable to that each stage costs two buffers and one flip-flop. Besides, the metempsychosis time will be increased and in a result it magnate be not feasible to work in a trunk. 5 2. 4 Gated ring oscillator (GRO) TDC Fig. 8. Gated ring oscillator TDC 6 The GRO TDC could achieve large dynamic range with miniscule number of delay elements. It measures the number of delay element transitions during measurement interval. By preserving the oscillator state at the end of the measurement interval k? , the quantization phantasm k? 1, from that measurement is also preserved. In fact, when the spare-time activity measurement of k? 1 is initiated, the previous quantization error is carried over as k = k? 1. This results in first- coiffure noise shaping of the quantization error in the frequency domain. Apart from the quantization noise, agree to the sanitary-known set shift algorithm for dynamic element matching, GRO TDC building realizes first order shaping of twin error 6. Thus, we can expect that this architecture ideally achieve high resolution without calibration even in the carriage of large mismatch. 6 3 System level design 3. 1 GoalThe proposed TDC is intentional to work with a 5GHz DCO and a 20MHz reference introduce while the circuit is fabricated in 65nm IBM CMOS technology the supply potential drop is 1. 2V and increase environment is Cadence 6. 1. 3. Fig. 9. Test bench for measuring rising/ dropping time of stimulus of T DC In order to find out the rising/falling time of the infix signal for TDC, the 5GHz sine wave signal which is the akin as the output of DCO in ADPLL is put by the inverter with the smallest size and the rising/falling time of the output of inverter is measured (Fig. 9) . 7 Fig. 10. Input and output of inverter Rising/falling time = 16. 58ps. This value is applied to pretence the practical case of input signals for TDC.The purpose for putting the sinusoid signal generated from DCO passing through and through with(predicate) the smallest inverter is to model the worst case for TDC with weakest cause ability. As the system level simulation result of ADPLL presents, the dynamic range of TDC is 20ps. The converter resolution is indispensable to be around 2ps meanwhile the power consumption should be unplowed as low as possible. Since in the occupation of this ADPLL, sub-gate resolution and small dynamic range are targeted, two lovelys of topologies of TDC are proposed. One is Vernier delay line TDC and the different one is parallel TDC. The comparison of these two architectures is concluded and both of them are designed on schematic level. 8 3. 2 Vernier delay line TDCStart Matched delay cell1 EN EN_ Delay1 Delay1 Delay1 Start_ Matched delay cell1 D Q D_ CLK Delay1 D Q0 D_ CLK Delay1 Delay1 D Q26 D_ CLK Stop Fig. 11. Diagram of Vernier delay line TDC 200ps Matched delay cell2 Delay2 Delay2 Delay2 start 20ps stop alter Valid output 2ns TDC_output Fig. 12. Timing of the interfaces of Vernier TDC As the description about Vernier TDC before, the start signal and stop signal are propagated by two delay line with small delay difference each stage respectively. The clock gating technology controlled by enable signal is used to realize low power waste material. The timing relationship of interfaces is described in Fig. 2 which indicates that enable signal should be set to high value half 9 cycle of start signal ahead of the stop rising edge and the revoluti on time is about 2ns. The delay time of each stage in TDC is about 60ps to 70ps and 27 stages are design to cover the whole dynamic range so that the conservative adherence of alteration time of TDC would be no more than 2ns. The next stage of TDC in ADPLL should sample the output when it is stable. Since the period of FREF is 50ns which federal agency that the instance of measurement occur every 50ns, it is soilable to adopt the method of serial conversion and prepare the valid output entropy after 2ns delay. 3. 3Parallel TDC Start Current Staved delay cell EN EN_ Start_ Current Starved delay cell D Q0 D_ CLK Stop Fig. 13. Diagram of parallel TDC Delay1 Delay2 Delay12 D Q1 D_ CLK D Q11 D_ CLK 10 200ps 20ps start stop enable Valid output 420ps TDC_output Fig. 14. Timing of the interfaces of parallel TDC Configuring the gates not in a chain but in parallel generates TDC depicted in Fig. 13. The start signal applied to all delay elements in parallel. On the rising of stop signal the outputs of all delay elements are sampled at the same time. Instead of propagating the differential start signal, stop signal is delayed to avoid differential mismatch problem.The delay cells connected to stop signal are sized for delays = 0+? ?N =? . The time difference surrounded by the delayed stop signal is quantize with a resolution The conversion results are available immediately after the rising of stop signal. 3. 4 Performance comparison Parallel TDC Parallel delay elements with gradually increase propagation delays are simultaneously sampled on the arrival of stop signal. No loop mental synthesis feasible Sub-gate resolution Conversion time independent from resolution Susceptible to variations Not feasible to high dynamic range Careful layout design Vernier TDC doctrine Start and stop signals propagate along two delay lines with slightly different delays.Loop structure Pros Loop structure possible Sub-gate resolution standard structure High dynamic range possible w ith loop structure Differential delay lines Conversion time depends on measurement interval and resolution Cons Table1. Performance comparison between Vernier TDC and parallel TDC 11 4 Schematic design and simulation 4. 1 Sense Amplifier Based Flip-Flop Flip-Flops are critical to the performance of Time to Digital Converter due(p) to the tight timing constraints and low power requirements. Metastability is a physical phenomenon that limits the performance of comparators and digital sampling elements, such as latches and flip-flops. It recognizes that it akes a nonzero amount of time from the start of a sampling event to determine the input level or state 15. This resolution time gets exponentially big if the input state change gets close to the sampling event. In the limit, if the input changes at exactly the same time as the sampling event, it might theoretically take an infinite amount of time to go down. During this time, the output can dwell in an illegal digital state somew here between zero and one. However, this flip flop is supposed to be reprocessd in ADPLL so that the metastable condition of the retimed reference clock CKR is not acceptable. One reason is that the metastability of every clock could introduce glitches and double clocking in the digital logic circuitry being driven.The other reason is that it is quite likely that within a certain metastability window between FREF and CKV, the clock to Q delay of the flip flop would have the say-so to make CKR span multiple DCO clock periods. This amount of uncertainty is not acceptable for proper system action 4. For the application of TDC, due to that the metastability sampling window should be no larger than the high resolution to avoid bubbles in TDC code 7, mavend amplifier based flip-flop (SAFF) is chosen. 12 VDD MP1 MP2 MP3 MP4 MN3 VDD MN4 D MN1 MN5 MN2 D_ CLK MN6 Pulse Generator Symmetrical SR latch S_ S R VDD R_ MP7 MP8 MP5 MP6 MP9 Q MP10 Q_ MN9 MN10 MN7 MN11 MN12 MN8 Fig. 15. Symmetric SAFF The SAFF shown as Fig. 5 consists of sense amplifier in the first stage and SR latch in the second stage. The amplifier senses complementary differential inputs and produces monotonous transitions from high to low logic level on one of the outputs following the atomic number 82 clock edge. The SR latch conveys each transition and binds the state until the next leading clock arrives 8. When CLK is low, S_ and R_ are charged to high level through MP1 and MP4 meanwhile MN6 is closed. If D is high, S_ will be discharged through MN3, MN1 and MN6 which is opened by clock leading edges. Accordingly, R_ is hold to high level and Q is high in this case. The additional transistor MN5 is used to provide the discharging patch to ground. For example, when 13 ata is changed as CLK is high which means D is low and D_ is high at this time, S_ would be charging to high level if there is no MN5. However, S_ could be discharged through MN3, MN5, MN2 and MN6 since MN5 provides another mode to g round. Although SR latch is able to lock the state of outputs of sense amplifier, MN5 prevents potential charging caused by leakage genuine even after the input entropy is changed and therefore guarantee the stable outputs of flip-flop. The SR latch, as the output stage, is kind of symmetric profits topology with equivalent pull-up and pulldown transistors network. Q+ = S + R_Q Q_+ = R + S_Q_ In the equations above, Q represents a current sate and Q+ represents a future state after the transition of clock.Thus this circuit has equal delays of outputs and provides identical resolution of the rising and falling meta-stability of their input selective information. In addition, the data input capacitive fill uping is nevertheless one NMOS transistor and the interconnect capacitance parasitical is minimized. 4. 1. 1 Schematic design The basic principles of the SAFF design are that the size of the input transistors should be small comely to minimize the load effect of SAFF and l arge sufficient to stop the speed of it. The PMOS and NMOS networks should be matched and the sizes of transistors are adjusted to obtain equal delay of differential outputs. Fig. 16. Schematic of SAFF 14 Fig. 17. Schematic of Sense Amplifier Fig. 18. Schematic of symmetric SR latch 15 4. 1. 2 Sampling window simulation Fig. 19.Test bench of SAFF The ideal switch is used to initialize the output signal Q other Q will be floating at the lineage of simulation which would result in unpredictable rising or falling edge at the beginning therefore make it difficult to measure a fixed number of signal transition edge. In the practical case, the initial value of inputs of flip flop is either zero or one. The simulation is performed by tuning the delay time of CLK in order to change the time interval between CLK and D/D_. There are several cases simulated to verify the timing constraints of SAFF including setup timing, hold timing and sample window. 1. Normal sampling 16 Fig. 20. Normal Sampling Case Data D changes from zero to one and then is sampled after it is stable for a while. The crossing point of Q and Q_ is around 600mV which means there are equal delay of clock to Q and clock to Q_ due to the symmetric topology of SAFF. 2.Setup time simulation Setup time is the minimum time forward to triggering edge of the clock pulse up to which the data should be kept stable at flip flop input so that data could be properly sampled. This is due to the input capacitance present at the input. It takes some time to charge to the particular logic level at the input. During the simulation, the input data is changing from low to high and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 17 Fig. 21. Extreme case of sampling for setup time simulation The clock to Q delay is increasing exponentially when input data is approaching the clock triggering edge.When the data comes later than clock edge for 15ps, th e clock to Q delay is up to about 280ps shown in Fig. 21. If the data comes even later than this, the output of flip flop will enter into metastable state or will never output high value. 3. Hold time simulation Hold time is the minimum time after the clock edge up to which the data should be kept stable in order to trigger the flip flop at right voltage level. This is the time taken for the various switching elements to transit from saturation to melt off off and vice versa. During the simulation, the input data is changing from high to low and high value is supposed to be sampled. Sweep the position of CLK to find out when SAFF cannot capture the correct data. 18 Fig. 22.Extreme case of sampling for hold time simulation The clock to Q delay is increasing exponentially if transition of input data from one to zero happens close to the clock edge. As long as the data could keep stable long enough the flip flop is capable of recognizing it during limit time interval. The hold timing constraint is that data should be stable after the clock rising at least 16ps (Fig. 22) to guarantee flip-flop could sample the right value otherwise the flip flop will enter into illegal state or never output high value. 4. Sampling window 19 2. 9 2. 8 2. 7 2. 6 x 10 -10 Tclk-Q 2. 5 setup time 2. 4 2. 3 2. 2 2. 1 2 -0. 5 hold time 0 0. 5 1 1. 5 2 Tdata-clk 2. 5 3 3. 5 x 10 4 -11 Fig. 23. Sampling window simulationSampling window is delimitate as the time interval in which the flip-flop samples the data value. During the interval any change of data is prohibited in order to ensure robust and reliable operation 8. The flip-flop delay increases as the signal approaches the point of setup and hold time violation until the flip-flop fails to capture the correct data 9 which is displayed in Fig. 23. Metastability is modeled in critical flip-flops by continuous inspection of the timing relationship between the data input and clock pins and producing an unknown output on the data output p in if the delay to clock skew falls within the forbidden metastable window. Referring to Fig. 3, the metastable window is outlined as an x-axis region such that the clock to Q delay on the y-axis is long-lived by a certain amount than the nominal clock to Q delay. For example, if the nominal clock to Q delay is 200ps when the data to clock timing is far from critical, the metastability window would be 15ps if one can tolerate clock to Q delay increase by 20ps. If one can tolerate a high clock to Q delay increase of 30ps, the metastable window would drop to 6 ps. A question could be asked as to how far this window can extend. The point of accumulation lies in the fact that for a tight data to clock skew, the noise or other statistical uncertainty, such as jitter, could arbitrarily resolve the output such that the input data is missed.Therefore, for a conventional exposition of setup time, not only must the output be free of any metastable condition, but the input data have to be captured correctly. For this reason, the setup and hold times are conservatively defined in standard-cell libraries for an output delay increase of 10 or 20% over nominal. The specific nature of TDC vector capturing does not require this restrictive constraint. Here, any output-level resolution is satisfactory for proper operation as long as it is not metastable at the time of capture, and consequently, 20 the metastable window could be made arbitrarily small 1. This SAFF demonstrates very narrow sampling window less than 1ps according to the simulation results. 4. 2Vernier delay line TDC There are several components in Vernier delay line TDC including inverter, SAFF, matched delay cell, delay cell 1 and delay cell 2 in which matched delay cell has the same circuit topology with other two delay cells except that it has enable control pins. 4. 2. 1 Delay cells There are several methods to implement delay elements. The most popular terzetto methods for designing variable delay cells are shunt capacitor technique, current starved technique and variable transistor technique 10. In this thesis project, current starved delay element is employed because of its simple structure and relatively wide delay range of regulation.Vdd VBP M4 M2 M6 Vdd in C M1 M5 out VBN M3 Fig. 24. Current starved delay element As can be seen from the Fig. 24, there are two inverters between input and output of this circuit. The charging and discharging currents of the output capacitance of the first inverter, hoardd of M1and M2, are controlled by the transistors M3 and M4. Charging and discharging currents depend on the bias voltage of M3 and M4 respectively. In this delay element, both rising and 21 falling edges of input signal can be controlled. By increasing/decreasing the effective on resistance of controlling transistor M3 and M4, the circuit delay can be increased /decreased.Fig. 25. Schematic of Matched delay cell As the enable signal is set to high level, the input signal will pas s through this delay cell. The enable signal should be set to high level before the active edge of input signal comes. The differential start signal and stop signal passed through this delay cell to produce matched rising/falling edge signal for the next stage in TDC. With respect to design of the size of transistors, the input transistors of the delay cell should be relatively large to shield the load effect of SAFF meanwhile allow T5 to control the changing and discharging current through the capacitors of the first stage of inverter.The second stage of inverter should have enough driving ability for 5GHz input signals and therefore the sizes are specified large enough to withdraw sufficient current from power supply for transition. Due to that the differential signals are delayed, the delay cell is also required to have matched PMOS and NMOS networks to achieve equal delay time for rising or falling input signals. 22 Fig. 26. Schematic of delay cell 1 Fig. 27. Schematic of delay cell 2 23 The only difference between these two delay cells above is the size of transistor T5. The W/L ratio of T5 in delay cell 2 is a bit larger than delay cell 2 makes the delay of delay cell 2 is slightly shorter than delay cell 1. These two delay cells constitute two delay lines for Vernier TDC. Fig. 28.Schematic of Vernier delay line TDC This Vernier TDC includes 27 stages of delay cells for the reason that it should cover the dynamic range of 20ps and the additional bring out value introduced by the setup timing of SAFF. The first dumpy stage of delay cell is used to match the differential input signals for the following delay lines so that the input signals for each stage are characterized with the same rising or falling time. As a result, the delay difference between each delay pair for start and stop signal is only dependent on the different size of transistors in the current starved delay cell. 24 4. 2. 2 Simulation results The input of Vernier TDC, the delay difference between the start and stop signal, is move from 0 to 20ps.The resolution and linearity are work out and analyzed by conversion results from TDC. Fig. 29. Input of Vernier TDC (stop start) = 0ps Fig. 30. Input of Vernier TDC (stop start) = 20ps 25 The offset value of this TDC is 8 observed from Fig. 29. The result shown in Fig. 30 indicates that the start signal has passed through 22 stages of delay cells as the input is 20ps. Resolution = (20ps 0ps)/ (22 8) = 1. 43ps 25 20 Output of Vernier TDC (ps) 15 10 5 0 0 2 4 6 8 10 12 14 Input of Vernier TDC (ps) 16 18 20 Fig. 31. Vernier TDC transfer function 0. 6 0. 4 0. 2 DNL and INL LSB 0 -0. 2 -0. 4 -0. 6 -0. 8 -1 INL DNL 0 2 4 6 8 10 12 Input of Vernier TDC 14 16 18 20 Fig. 32. Vernier TDC linearity 26The Differential Non Linearity (DNL) is the divagation in the difference between two successive threshold points from 1LSB. entire Non Linearity (INL) is the deviation of the actual output. Both of them are calculated and inform in Fig. 32. The maximum DNL is +0. 4LSB while the maximum INL is -0. 89LSB. The process (skew) parameter files in the model directory contain the definition of the statistical distributions that represent the main process variations for the technology. This gives designers the susceptibility of testing their designs under many different process variations to ensure that their circuits perform as desired throughout the entire range of process specifications. This is a Monte Carlo approach to the chalk uping of designs.While being the most accurate test, it can also be time consuming to run enough simulations to obtain a valid statistical sample. Fig. 33. Monte Carlo simulation of the resolution for Vernier delay line TDC When running Monte Carlo to include FET mismatch, twain the Spectre mismatch and process vary statements are active. This will turn on both process and mismatch variations. Spectre provides the unique capability of running process variations independent of mismat ch variations. This capability is not back up for this release. The average resolution calculated by averaging the delay difference between two delay lines is around 1. 66ps. The average power over one period is 148. 1E-6 W.The maximum power consumption is about 3. 6mW and the conversion time is around 2ns which is in accordance with the interfacing time estimation in system level design. Since the enable signal closed the TDC after the conversion is completed, the start signal with high frequency is prohibited to propagate so as to eliminate the unnecessary transition of delay cells and in a result saving the power dissipation. 27 4. 3 4. 3. 1 Parallel TDC Delay cells In order to design a serial of delay cells with the equal difference of delay time used in parallel TDC, the size of the transistor in a current starved structure is swept. Fig. 34. Delay cell in Parallel TDC 28Fig. 35. Delay time Vs width of transistor T5 Unlike Vernier TDC, only stop signal is delayed by various de lay cells in parallel TDC. Thus the control of rising edge required, and then the size of transistor T5 is adjusted. As can be seen from Fig. 34, the size of transistors M1, M2, M4 and M5 is basically determined by the load capacitance which refers to the CLK pin of SAFF in this situation. Transistor T5 should be much smaller than M2 so that the discharging current could be controlled by T5. As the size of T5 increases, the delay time becomes smaller which means the delay cell is faster. According to the parameter analysis result in Fig. 5, the size of T5 can be determined by selecting the size like to the delay time with 2ps difference for a serial delay cells. Fig. 36. Schematic of Parallel TDC 29 As the analysis in system level design, the delay cells are sized for delays = 0 + ? ?N. The single stop signal is delayed in parallel TDC, therefore the matched delay cell connected to differential start signal is used to cancel the 0 and offset value. 4. 3. 2 Simulation results Simila rly to Vernier TDC simulation, the input of parallel TDC, the delay difference between the start and stop signal, is swept from 0 to 20ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 37.Input of parallel TDC (stop start) = 0ps 30 Fig. 38. Input of parallel TDC (stop start) = 20ps The offset value of this TDC is 1 observed from Fig. 37. The result shown in Fig. 38 indicates that the start signal has passed through 11 stages of delay cells as the input is 20ps. Resolution = (20ps 0ps)/ (11 1) = 2ps. 20 18 16 Output of parallel TDC (ps) 14 12 10 8 6 4 2 0 0 2 4 6 8 10 12 14 Input of parallel TDC (ps) 16 18 20 Fig. 39. Parallel TDC transfer function 31 1 INL DNL DNL and INL LSB 0. 5 0 -0. 5 0 2 4 6 8 10 12 Input of parallel TDC 14 16 18 20 Fig. 40. Parallel TDC linearity DNL and INL are calculated and reported in Fig. 40. The maximum DNL is +0. LSB while the maximum INL is 1LSB. The average power over one period is 87. 33E-6 W which is much smaller than Vernier TDC. The reason is that the clock gating technology controlled by enable signal eliminates the otiose transition of delay cells. As the system level design indicates, the parallel TDC only works for 420ps each period of stop signal because that the conversion is completed instantly due to the intrinsic characteristic of parallel TDC and therefore there is no power consumption during the rest time. Although the peak power consumption is approximately equivalent to Vernier TDC, the average power dissipation is decreased dramatically. 32 Layout and post-simulation 5. 1 Layout of SAFF and post-simulation For the layout of radio frequency circuit the interconnectedness parasitic will be a critical problem. In an audio frequency application for instance parasitic will probably be a minor concern. However, the operation frequency of this circuit is 5GHz which means that the interconnection parasitic will influence the performance of circuit dramatically. To m inimize this influence, we could move interconnections to higher metals and make the metals carry current rather than poly. Besides, the floor plan should be as compact as possible to optimize the parasitic and opposition of interconnections. GND T0Symmetric SR Latch T15 T14 T13 T8 T9 T5 T3 Q_ T1 T12 T10 T11 T7 Q T6 T4 T2 VDD T0 T2 T4 T3 T5 T9 T1 D T6 T7 D_ CLK T8 CLK GND Sensed Amplifier Fig. 41. Floor Plan of SAFF 33 There are several steps for floor plan. First step is to examine the size of transistors and relegate transistor size in a number of layout oriented fingers. Then identify the transistors than can be determined on the same stack according to the principles of using almost the same number of fingers per stack and put the transistors with common drain or computer address together. In the floor plan shown in Fig. 41, power line VDD is reused by SR latch and sensed amplifier to make the connections compact.Fig. 42. Layout of SAFF 34 In the festering environment of Ca dence 6. 1. 3, Calibre is used for DRC and Assura is used to do LVS check and RCX. Post-simulation is then performed with av_extracted view. Fig. 43. Post-simulation of sampling window Compared to Fig. 23, Fig. 43 illustrates that the timing constraint point moved from 16ps to 29ps which will affect the offset value of TDC. In addition, the delay time from clock leading edge to output Q is increased. However, this SAFF after layout can be employed to avoid meta-stability effectively due to that the sampling window is still less than 1ps. 5. 2 Layout of parallel TDC and post-simulationIn this TDC system, the clock distribution network formed as a tree distributes the signal to all the delay cells. To reduce the clock uncertainty, the network requires highly matched topology showed as Fig. 44 below. 35 Clock Fig. 44. Floor plan of Clock distribution This kind of topology guarantees the equal delay from the common point clock to each element. Fig. 45. Layout of parallel TDC After DRC a nd LVS, the RC net list is extracted to do post-simulation. The input of parallel TDC after layout, the delay difference between the start and stop signal, is swept from 0 to 30ps. The resolution and linearity are calculated and analyzed by conversion results from TDC. Fig. 46.Input of parallel TDC after layout (stop start) = 0ps 36 Fig. 47. Input of parallel TDC after layout (stop start) = 30ps The offset value of this implemented TDC is 0 observed from Fig. 46. The result shown in Fig. 47 indicates that the start signal has passed through 10 stages of delay cells as the input is 30ps. Resolution = (30ps 0ps)/ (10 0) = 3ps. 35 30 Output of parallel TDC after layout (ps) 25 20 15 10 5 0 0 5 10 15 20 Input of parallel TDC after layout (ps) 25 30 Fig. 48. Parallel TDC transfer function after layout 37 0. 5 0. 4 0. 3 DNL and INL after layout LSB 0. 2 0. 1 0 -0. 1 -0. 2 -0. 3 -0. 4 -0. 5 INL DNL 0 5 10 15 20 Input of parallel TDC (ps) 25 30 Fig. 49.Parallel TDC linearity after layou t DNL and INL are calculated and reported in Fig. 49. The maximum DNL is 0. 33LSB while the maximum INL is 0. 5LSB. The average power over one period is 442. 1E-6 W. The maxim total current is about 3. 24mA. The peak power consumption is almost the same as the TDC before layout, but there are obvious ripples even the TDC is disabled due to that the parasitic capacitors increase the time for charging and discharging. 5. 3 Comparison and analysis Technique Parallel 2-level DL parallel Pseudo-diff DL VernierGRO CMOS m 0. 065 0. 35 0. 13 0. 09 0. 09 Supply V 1. 2 3 1. 2 1. 3 1. 2 Power mW 3. 89 50 2. 5 6. 9 4. 32 Resolution ps 3 24 12 17 6. 4 INL/DNL 0. 5/0. 3 -1. 5/0. 55 -1. 15/1 0. 7/0. 7 Work This 12 3 7 13 Table2. Comparison to previous work Table2 compares the proposed TDC to prior produce work in CMOS technology. This TDC features the fastest resolution with the best linearity. The power consumption is not directly comparable because the results from the other works are correspo nding to different input range. However, it still indicates that this TDC consumes very low power due to that the start signal 38 only passes two buffers and the stop signal with low frequency is delayed. The TDC error has several components quantization, linearity and randomness due to thermal effects.As can be seen from table5, the implemented TDC achieves medium linearity which can be alter if the layout is enhanced from floor plan considering the parasitic effects. With respect to quantization noise, the total noise power generated from this kind of TDC is spread uniformly over the span from dc to the Nyquist frequency without modulation. As a result, the proposed TDC contributes the last noise floor due to high resolution. = =3ps, , = 20MHz, we obtain = -104. 3 dBc/Hz. Banerjees figure of merit (BFM) 14, being a 1-Hz normalized phase noise floor, is defined as BFM = where is a sampling frequency of the phase comparison and N= is the frequency division ratio of a PLL.It is use d to compare the phase performance of PLLs with different reference frequencies and division ratios. In this TDC based ADPLL, BFM = -225. 3dB. level(p) though state-of-the-art conventional PLLs implemented in a SiGe process can outperform the ADPLL presented here in the in band phase noise, -213 dB in reference and -218 dB in reference, the worst case BFM of -205 dB appears adequate even for GSM applications, since there are no other significant phase-noise contributions as in the conventional PLLs 4. However, the Gated Ring Oscillator TDC is able to aim most of the noise to high frequency region which is then filtered by the loop filter in ADPLL through holding oscillation client state between measurements.The obvious drawback of this TDC is that the dynamic range is relatively small which will limit the application of it. Parallel TDC is not feasible to compose the loop structure so that the area and power dissipation will be increased dramatically if larger dynamic range is re quired. unless the Vernier TDC designed in this thesis can be used in the loop structure for large dynamic range. 39 6 Conclusion In this thesis, two kinds of Time to Digital Converters are designed with Vernier and parallel structure on schematic level respectively. The performance of these two TDCs are concluded and compared. In the Vernier TDC, only two delay cells are designed and then reused to constitute two delay lines with slightly different delay time.This architecture is easy to implement and reduces the mismatch with delay cells. But the conversion time dependent on resolution and measurement interval time is relatively long since the signals are propagating along the delay cells in serial. On the other hand, in parallel TDC, the process of conversion is completed instantaneously due to that the signals are passing through the delay cells and then captured in parallel. Thus it has lower average power dissipation over one period. However, a set of delay cells are designed which obviously introduce nonlinearities. To minimize the mismatch problem, the single stop signal is delayed instead of two input signals for avoiding the differential mismatch situation.To sum up, both of the TDCs achieve sub-gate resolution which is able to meet the application requirements and Vernier TDC has higher resolution and better linearity but longish conversion time and larger power consumption compared to parallel TDC according to the simulation results. The parallel TDC is chosen to be implemented on layout. compare the results from schematic simulation and post-simulation, the performance is decreased on resolution, linearity and power consumption after layout. The major reason for this phenomenon is the parasitic capacitance of transistors and real fits which is a significant factor to affect the final properties in high frequency circuits.In the stage of schematic design, the sizes of transistors are not fully considered and results in difficulties on floor pla n of layout. Specifically, the transistors are rather difficult to split into the same fingers per stack and therefore the floor plan is not compact enough to minimize the interconnections. Besides, the parasitic capacitance should have been emulated on schematic simulation in order to predict the effect after layout otherwise it would be very time consuming if the schematic design is modify after layout. In addition, the size of transistors is very small which makes them comparable to wire parasitic effects. Although small transistors are with smaller parasitic capacitance and less power consumption, they will more sensitive to layout mismatch.The function of the TDCs designed and implemented in the thesis is guaranteed for the application but the performance needs to be improved. The layout turns out to be an essential stage for the final characteristics of the circuits. With a more thoughtful design flow and sophisticated consideration for mismatch, the circuits after layout cou ld maintain the performance as schematic level. 40 7 Future work There is plenty of more work to be done to improve the performance of TDC. Due to that the TDC is essential to the aggressive goal of phase noise from all digital PLL, other kinds of architectures of it are worth to try for the required resolution and dynamic range. Since the performance of circuit after layout is not identical with schematic, the size of transistors could be modified for layout oriented. To reduce the parasitic effects, layout should be improved from a better floor plan. Vernier TDC with higher resolution and better linearity could be implemented on layout which can tolerate first order PVT variation if two delay chains are well matched 11. Although the Vernier TDC and parallel TDC achieve high resolution, they have very low efficiency when measuring large time intervals, which requires extra hardware and power consumption. To overcome this limitation, a Vernier Ring TDC has been proposed recently.Unl ike the conventional Vernier TDC, this novel TDC places the Vernier delay cells in a ring format such that the delay chains can be reused for measuring large time intervals. Digital logic monitors the number of laps the signals propagate along the rings. Arbiters are used to record the location where the lag signal catches up with the lead signal. The reuse of Vernier delay cells in a ring configuration achieves fine resolution and large detectable range simultaneously with small area and low power consumption 11. This architecture of Vernier Ring TDC combines the Vernier delay lines and GRO topology is worth to implement for wide application. ? ? 41 8 1 2 3 4 5 6 7